Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics
Crossref DOI link: https://doi.org/10.1007/978-981-13-8942-9_39
Published Online: 2019-09-25
Published Print: 2020
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Loganathan, Haripriya
Rohit, Patnaikuni
Suneel, Polamarasetty Sai
Balasubramanian, Karthi
Text and Data Mining valid from 2019-09-25
Chapter History
First Online: 25 September 2019