Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of $$512 \times 512$$ 512 × 512 Frames
Crossref DOI link: https://doi.org/10.1007/s00034-016-0315-6
Published Online: 2016-04-23
Published Print: 2017-02
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Mukherjee, Rohan
Biswas, Baishik
Chakrabarti, Indrajit
Dutta, Pranab Kumar
Sengupta, Somnath
Ray, Ajoy Kumar
Text and Data Mining valid from 2016-04-23