Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA
Crossref DOI link: https://doi.org/10.1007/s00034-016-0335-2
Published Online: 2016-05-24
Published Print: 2017-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Arish, S.
Sharma, R. K.
Text and Data Mining valid from 2016-05-24