An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm
Crossref DOI link: https://doi.org/10.1007/s00034-020-01436-4
Published Online: 2020-05-07
Published Print: 2020-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kavitha, M. S.
Rangarajan, P.
Text and Data Mining valid from 2020-05-07
Version of Record valid from 2020-05-07
Article History
Received: 6 November 2019
Revised: 21 April 2020
Accepted: 22 April 2020
First Online: 7 May 2020
Compliance with Ethical Standards
:
: Authors declare that they have no conflict of interest