A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS
Crossref DOI link: https://doi.org/10.1007/s00034-021-01861-z
Published Online: 2021-11-10
Published Print: 2022-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Sahani, Jagdeep Kaur
Singh, Anil http://orcid.org/0000-0002-8087-1708
Agarwal, Alpana
Text and Data Mining valid from 2021-11-10
Version of Record valid from 2021-11-10
Article History
Received: 12 April 2021
Revised: 20 September 2021
Accepted: 21 September 2021
First Online: 10 November 2021