Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate
Crossref DOI link: https://doi.org/10.1007/s00339-020-03869-9
Published Online: 2020-08-07
Published Print: 2020-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Singh, Ashish Kumar
Tripathy, Manas Ranjan
Baral, Kamalaksha
Singh, Prince Kumar
Jit, Satyabrata http://orcid.org/0000-0001-6772-8117
Text and Data Mining valid from 2020-08-07
Version of Record valid from 2020-08-07
Article History
Received: 31 March 2020
Accepted: 30 July 2020
First Online: 7 August 2020