A low-jitter all-digital PLL with high-linearity DCO
Crossref DOI link: https://doi.org/10.1007/s00542-018-4252-0
Published Online: 2018-12-10
Published Print: 2021-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Lo, Yu-Lung
Wang, Hsi-Hua
Li, Yu-Hsin
Fan, Fang-Yu
Yu, Chun-Yen
Liu, Jen-Chieh http://orcid.org/0000-0002-7045-6586
Text and Data Mining valid from 2018-12-10
Version of Record valid from 2018-12-10
Article History
Received: 31 May 2018
Accepted: 3 December 2018
First Online: 10 December 2018