FPGA friendly NoC simulation acceleration framework employing the hard blocks
Crossref DOI link: https://doi.org/10.1007/s00607-020-00901-x
Published Online: 2021-01-16
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Prasad, B. M. Prabhu http://orcid.org/0000-0002-6138-3012
Parane, Khyamling
Talawar, Basavaraj
Funding for this research was provided by:
Ministry of Electronics and Information technology (DIC/MUM/GA/10(37)D)
Text and Data Mining valid from 2021-01-16
Version of Record valid from 2021-01-16
Article History
Received: 26 September 2020
Accepted: 30 December 2020
First Online: 16 January 2021