A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application
Crossref DOI link: https://doi.org/10.1007/s10470-015-0552-9
Published Online: 2015-05-09
Published Print: 2015-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kim, Hongjin
Lee, DongSoo
Lee, Juri
Oh, SeongJin
Tiwari, Honey Durga
Pu, YoungGun
Lee, Kang-Yoon
Text and Data Mining valid from 2015-05-09