A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology
Crossref DOI link: https://doi.org/10.1007/s10470-015-0613-0
Published Online: 2015-07-29
Published Print: 2015-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Jeon, Min-Ki
Yoo, Changsik
Funding for this research was provided by:
KEIT (Korea Evaluation Institute of Industrial Technology) (10044451)
National Research Foundation of Korea (NRF) (2013R1A2A2A01004958)
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