Delay analysis of buffer inserted sub-threshold interconnects
Crossref DOI link: https://doi.org/10.1007/s10470-016-0860-8
Published Online: 2016-09-09
Published Print: 2017-02
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Dhiman, Rohit
Chandel, Rajeevan
License valid from 2016-09-09