Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme
Crossref DOI link: https://doi.org/10.1007/s10470-019-01576-x
Published Online: 2020-01-01
Published Print: 2020-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Sribhuvaneshwari, H.
Kannan, Suthendran
Text and Data Mining valid from 2020-01-01
Version of Record valid from 2020-01-01
Article History
Received: 16 July 2019
Revised: 21 October 2019
Accepted: 13 December 2019
First Online: 1 January 2020