Clock delay-based design for hysteresis programming and noise reduction in dynamic comparators
Crossref DOI link: https://doi.org/10.1007/s10470-020-01656-3
Published Online: 2020-04-30
Published Print: 2021-02
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Khanfir, Leila
Mouine, Jaouhar
Text and Data Mining valid from 2020-04-30
Version of Record valid from 2020-04-30
Article History
Received: 1 July 2019
Revised: 30 December 2019
Accepted: 10 April 2020
First Online: 30 April 2020