Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction
Crossref DOI link: https://doi.org/10.1007/s10470-020-01670-5
Published Online: 2020-06-11
Published Print: 2020-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Meenakshi Vidya, P.
Sudha, S.
Text and Data Mining valid from 2020-06-11
Version of Record valid from 2020-06-11
Article History
Received: 17 April 2020
Revised: 17 April 2020
Accepted: 30 May 2020
First Online: 11 June 2020