A 350 mV, 2 MHz, 16-kb SRAM with programmable wordline boosting in the 65 nm CMOS technology
Crossref DOI link: https://doi.org/10.1007/s10470-021-01907-x
Published Online: 2021-07-12
Published Print: 2021-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Nabavi, Morteza http://orcid.org/0000-0001-7960-471X
Sachdev, Manoj
Text and Data Mining valid from 2021-07-12
Version of Record valid from 2021-07-12
Article History
Received: 7 December 2020
Revised: 27 April 2021
Accepted: 21 June 2021
First Online: 12 July 2021