Asymmetrically reliable caches for multicore architectures under performance and energy constraints
Crossref DOI link: https://doi.org/10.1007/s10586-016-0641-2
Published Online: 2016-09-17
Published Print: 2016-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Arslan, Sanem
Topcuoglu, Haluk Rahmi
Kandemir, Mahmut Taylan
Tosun, Oguz
License valid from 2016-09-17