Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates
Crossref DOI link: https://doi.org/10.1007/s10586-018-2552-x
Published Online: 2018-03-26
Published Print: 2019-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Naveen Balaji, G.
Chenthur Pandian, S.
Text and Data Mining valid from 2018-03-26
Article History
Received: 23 February 2018
Revised: 26 February 2018
Accepted: 14 March 2018
First Online: 26 March 2018