Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism
Crossref DOI link: https://doi.org/10.1007/s10617-016-9174-4
Published Online: 2016-03-17
Published Print: 2016-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Brandalero, Marcelo http://orcid.org/0000-0002-0012-7023
Beck, Antonio Carlos S.
Text and Data Mining valid from 2016-03-17