Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs
Crossref DOI link: https://doi.org/10.1007/s10836-014-5463-7
Published Online: 2014-07-12
Published Print: 2014-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Ullah, Anees
Sterpone, Luca
Text and Data Mining valid from 2014-07-12