Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology
Crossref DOI link: https://doi.org/10.1007/s10836-015-5549-x
Published Online: 2015-11-14
Published Print: 2015-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Li, Lixiang
Li, Yuanqing
Wang, Haibin
Liu, Rui
Wu, Qiong
Newton, Michael
Ma, Yuan
Chen, Li
Text and Data Mining valid from 2015-11-14