A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores
Crossref DOI link: https://doi.org/10.1007/s10836-016-5578-0
Published Online: 2016-03-01
Published Print: 2016-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Wali, I.
Virazel, Arnaud
Bosio, A.
Girard, P.
Pravossoudovitch, S.
Reorda, M. Sonza
Text and Data Mining valid from 2016-03-01