Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering
Crossref DOI link: https://doi.org/10.1007/s10836-016-5593-1
Published Online: 2016-05-28
Published Print: 2016-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Zamanzadeh, Sharareh
Jahanian, Ali
Text and Data Mining valid from 2016-05-28