A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs
Crossref DOI link: https://doi.org/10.1007/s10836-016-5599-8
Published Online: 2016-07-11
Published Print: 2016-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Renaud, Guillaume
Barragan, Manuel J.
Laraba, Asma
Stratigopoulos, Haralampos-G.
Mir, Salvador
Le-Gall, Hervé
Naudet, Hervé
License valid from 2016-07-11