Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation
Crossref DOI link: https://doi.org/10.1007/s11220-020-00308-0
Published Online: 2020-08-17
Published Print: 2020-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Priyanka, E. B. http://orcid.org/0000-0001-7280-9309
Thangavel, S.
Pratheep, V. G.
Text and Data Mining valid from 2020-08-17
Version of Record valid from 2020-08-17
Article History
Received: 3 April 2020
Revised: 26 June 2020
First Online: 17 August 2020