Reliability aware throughput management of chip multi-processor architecture via thread migration
Crossref DOI link: https://doi.org/10.1007/s11227-016-1665-3
Published Online: 2016-02-18
Published Print: 2016-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Pouyan, Fatemeh
Azarpeyvand, Ali
Safari, Saeed
Fakhraie, Sied Mehdi
Text and Data Mining valid from 2016-02-18