Time-sensitivity-aware shared cache architecture for multi-core embedded systems
Crossref DOI link: https://doi.org/10.1007/s11227-019-02891-w
Published Online: 2019-05-18
Published Print: 2019-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Lee, Myoungjun http://orcid.org/0000-0001-9774-5276
Kim, Soontae
Funding for this research was provided by:
National Research Foundation of Korea (2018R1A2B2005277)
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Article History
First Online: 18 May 2019