Static probabilistic worst case execution time estimation for architectures with faulty instruction caches
Crossref DOI link: https://doi.org/10.1007/s11241-014-9212-x
Published Online: 2014-11-05
Published Print: 2015-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Hardy, Damien
Puaut, Isabelle
Text and Data Mining valid from 2014-11-05