A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal
Crossref DOI link: https://doi.org/10.1007/s11265-022-01810-2
Published Online: 2022-09-15
Published Print: 2022-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kumar, Lalit
Shrestha, Rahul http://orcid.org/0000-0003-2224-0892
Text and Data Mining valid from 2022-09-15
Version of Record valid from 2022-09-15
Article History
Received: 11 June 2021
Revised: 7 June 2022
Accepted: 10 August 2022
First Online: 15 September 2022