An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box
Crossref DOI link: https://doi.org/10.1007/s11277-016-3385-7
Published Online: 2016-06-03
Published Print: 2017-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Priya, Sridevi Sathya
Karthigaikumar, Palanivel
Siva Mangai, N. M.
Kirti Gaurav Das, P.
License valid from 2016-06-03