Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization
Crossref DOI link: https://doi.org/10.1007/s11277-017-5028-z
Published Online: 2017-10-31
Published Print: 2018-02
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Tomar, Geetam Singh
George, Marcus Lloyde
License valid from 2017-10-31