TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis
Crossref DOI link: https://doi.org/10.1007/s11390-022-1499-9
Published Online: 2022-11-30
Published Print: 2022-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Zhang, Yi-Fan
Sun, Lei
Cao, Qiang
Text and Data Mining valid from 2022-11-30
Version of Record valid from 2022-11-30
Article History
Received: 6 April 2021
Accepted: 12 April 2022
First Online: 30 November 2022