A Disturbance Rejection Control Approach for Clock Synchronization in IEEE 1588 Networks
Crossref DOI link: https://doi.org/10.1007/s11424-018-7050-y
Published Online: 2018-12-07
Published Print: 2018-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Zhang, Junhao
Zhang, Wenan
Text and Data Mining valid from 2018-12-01
Article History
Received: 22 February 2017
Revised: 7 September 2017
First Online: 7 December 2018