A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology
Crossref DOI link: https://doi.org/10.1007/s11432-014-5060-5
Published Online: 2014-05-07
Published Print: 2014-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Chen, HongMing
Cheng, YuHua
Text and Data Mining valid from 2014-05-07