A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
Crossref DOI link: https://doi.org/10.1007/s11432-014-5226-1
Published Online: 2014-12-10
Published Print: 2014-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Chen, HongMing
Ma, Song
Wang, Liu
Zhang, Hao
Pan, KenYi
Cheng, YuHua
Text and Data Mining valid from 2014-12-01