Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
Crossref DOI link: https://doi.org/10.1007/s11432-015-5455-y
Published Online: 2016-02-01
Published Print: 2016-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Lu, Guangyi
Wang, Yuan
Zhang, Lizhong
Cao, Jian
Zhang, Xing
Text and Data Mining valid from 2016-02-01