Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
Crossref DOI link: https://doi.org/10.1007/s11432-019-2658-x
Published Online: 2020-05-20
Published Print: 2020-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Dong, Xiaoqiao
Li, Ming
Zhang, Wanrong
Yang, Yuancheng
Chen, Gong
Sun, Shuang
Wang, Jianing
Xu, Xiaoyan
An, Xia
Text and Data Mining valid from 2020-05-20
Version of Record valid from 2020-05-20
Article History
Received: 7 April 2019
Revised: 28 June 2019
Accepted: 9 September 2019
First Online: 20 May 2020