Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors
Crossref DOI link: https://doi.org/10.1007/s11554-016-0606-y
Published Online: 2016-05-31
Published Print: 2017-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Rodríguez-Sánchez, Rafael
Quintana-Ortí, Enrique S.
Funding for this research was provided by:
Ministerio de Economía y Competitividad (CICYT TIN2011-23283, CICYT TIN2014-53495-R)
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