A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition
Crossref DOI link: https://doi.org/10.1007/s11554-019-00901-x
Published Online: 2019-07-25
Published Print: 2020-10
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Chakraborty, Anirban
Banerjee, Ayan
Text and Data Mining valid from 2019-07-25
Version of Record valid from 2019-07-25
Article History
Received: 20 November 2018
Accepted: 15 July 2019
First Online: 25 July 2019