Impact of Noise and Interface Trap Charge on a Heterojunction Dual-Gate Vertical TFET Device
Crossref DOI link: https://doi.org/10.1007/s11664-024-10927-y
Published Online: 2024-02-07
Published Print: 2024-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Nasani, Karthik http://orcid.org/0000-0002-6370-2072
Bhowmick, Brinda
Pukhrambam, Puspa Devi
Text and Data Mining valid from 2024-02-07
Version of Record valid from 2024-02-07
Article History
Received: 14 July 2023
Accepted: 9 January 2024
First Online: 7 February 2024
Declarations
:
: The authors declare that they have no conflicts of interest.