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CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

Crossref DOI link: https://doi.org/10.1038/s41467-023-41868-5

Published Online: 2023-09-28

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Wang, Wenhui

Li, Ke

Lan, Jun https://orcid.org/0000-0003-4824-8243
Shen, Mei

Wang, Zhongrui https://orcid.org/0000-0003-2264-0677
Feng, Xuewei

Yu, Hongyu

Chen, Kai

Li, Jiamin

Zhou, Feichi https://orcid.org/0000-0001-7756-1082
Lin, Longyang https://orcid.org/0000-0002-4702-737X
Zhang, Panpan https://orcid.org/0009-0000-5449-2176
Li, Yida https://orcid.org/0000-0002-5675-582X
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Text and Data Mining valid from 2023-09-28

Version of Record valid from 2023-09-28
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Article History

Received: 24 May 2023

Accepted: 14 September 2023

First Online: 28 September 2023

Competing interests

: The authors declare no competing interests.