Valley-engineered ultra-thin silicon for high-performance junctionless transistors
Crossref DOI link: https://doi.org/10.1038/srep29354
Published Online: 2016-07-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kim, Seung-Yoon
Choi, Sung-Yool
Hwang, Wan Sik
Cho, Byung Jin
Text and Data Mining valid from 2016-07-08
Version of Record valid from 2016-07-08
Article History
Received: 5 March 2016
Accepted: 16 June 2016
First Online: 8 July 2016
Competing interests
: The authors declare no competing financial interests.