Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit
Crossref DOI link: https://doi.org/10.1134/S106373971903003X
Published Online: 2019-06-13
Published Print: 2019-05
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Cheremisinov, D. I.
Cheremisinova, L. D.
Text and Data Mining valid from 2019-05-01
Version of Record valid from 2019-05-01
Article History
Received: 20 November 2018
Revised: 3 December 2018
Accepted: 3 December 2018
First Online: 13 June 2019