Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate
Crossref DOI link: https://doi.org/10.1134/S1063739719030065
Published Online: 2019-06-13
Published Print: 2019-05
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Ivanova, G. A.
Ryzhova, D. I.
Gavrilov, S. V.
Vasilyev, N. O.
Stempkovskii, A. L.
Text and Data Mining valid from 2019-05-01
Version of Record valid from 2019-05-01
Article History
Received: 20 November 2018
Revised: 3 December 2018
Accepted: 3 December 2018
First Online: 13 June 2019