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An Efficient Technique to Design Ternary Logic Schematics with Pseudo N-GNRFETs

Published Online: 2025-03-04

Published Print: 2024-12

Authors

Raghu Ramaiah, P.

Basha, Shaik Javid

Rao, Y. Mallikarjuna
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Text and Data Mining valid from 2024-12-01

Version of Record valid from 2024-12-01
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Article History

Received: 29 May 2024

Revised: 20 October 2024

Accepted: 20 October 2024

First Online: 4 March 2025

CONFLICT OF INTEREST

: The authors of this work declare that they have no conflicts of interest.

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