The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture
Crossref DOI link: https://doi.org/10.1134/S0361768817060032
Published Online: 2017-12-16
Published Print: 2017-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Batuzov, K. A.
License valid from 2017-11-01