Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length
Crossref DOI link: https://doi.org/10.1134/S1063782620110111
Published Online: 2020-11-02
Published Print: 2020-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Sanjay,
Prasad, B.
Vohra, Anil
Text and Data Mining valid from 2020-11-01
Version of Record valid from 2020-11-01
Article History
Received: 6 July 2020
Revised: 6 July 2020
Accepted: 17 July 2020
First Online: 2 November 2020
CONFLICT OF INTEREST
: The authors declare that they have no conflict of interest.