A scalable architecture for quantum information processors: qubit partitioning, placement, and scheduling for minimized circuit latency
Crossref DOI link: https://doi.org/10.1140/epjqt/s40507-026-00519-6
Published Online: 2026-05-13
Published Print: 2026-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Alimohammadi, Zahra
Mohammadzadeh, Naser
Seyedi, Saeid
Abdoli, Hatam
Text and Data Mining valid from 2026-05-13
Version of Record valid from 2026-05-18
Article History
Received: 20 February 2026
Accepted: 5 May 2026
First Online: 13 May 2026
Declarations
:
: Not applicable.”
: The authors declare no competing interests.