An inter-FPGA communication bus with error detection and dynamic clock phase adjustment
Crossref DOI link: https://doi.org/10.1186/s13173-015-0026-z
Published Online: 2015-07-17
Published Print: 2015-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Melo, LT
Santana, SHC
Silva-Filho, AG
Lima, ME
Medeiros, VWC
Marinho, MLM
License valid from 2015-07-17