Threshold voltage and DIBL effect analysis and modeling for FD-SOI MOSFET with high k + SiO$_2$ gate
Crossref DOI link: https://doi.org/10.1360/N112017-00200
Published Online: 2019-03-15
Published Print: 2019-03-01
Update policy: https://doi.org/10.1360/scp-crossmark-policy-page
WAN, Luxu
YANG, Jianguo
KE, Daoming
WU, Di
YANG, Fei
CHEN, Tian