Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
Crossref DOI link: https://doi.org/10.1631/FITEE.1500293
Published Online: 2016-10-07
Published Print: 2016-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Geng, Liang
Shen, Ji-zhong
Xu, Cong-yuan
License valid from 2016-09-01